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| WM8143-10 10-bit/6msps ccd signal processor production data june 1998 rev 3f production data datasheets contain fina l s pecifications current on publication date. supply of products conforms to wolfson microelectronic's terms and conditions . wolfson microelectronics lutton court, bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk www: http://www.wolfson.co.uk 1998 wolfson microelectronics ltd. description the WM8143-10 integrates the analogue signal conditioning required by ccd sensors with a 10-bit adc. the WM8143-10 requires minimal external circuitry and provides a cost-effective sensor to digital domain system solution. each of the three analogue conditioning channels includes reset level clamp, cds, fine offset level shifting and programmable gain amplification. the three channels are multiplexed into the adc. the output from the adc is fed to the output bus pins op[9:0] via a 10/8 bit multiplexer, enabled by the oeb signal. the flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. the WM8143-10 can be configured for pixel-by-pixel or line-by-line multiplexing operation. reset level clamp and/or cds features can be optionally bypassed. the device configuration is programmed either via a simple serial interface or via an eight-bit parallel interface. the serial/parallel interfaces of the WM8143-10 are control compatible with those of the wm8144-10 and wm8144-12. features reset level clamp correlated double sampling (cds) fine offset level shifting programmable gain amplification 10-bit adc with maximum 6 msps simple clocking scheme control by serial or parallel interface time multiplexed eight-bit data output mode 32 pin tqfp package interface compatible with wm8144-10 and wm8144-12 applications flatbed scanners sheet feed scanners film scanners ccd sensor interfaces contact image sensor (cis) interfaces block diagram + + offset + + + + m u x rinp ginp binp timing control vsmp mclk rlc dgnd dvdd avdd 10-bit adc 10/8 mux configurable serial/parallel control interface sdi / dna sck / rnw sen / stb nreset oeb mux vmid vrlc vru vrt vrb vmid cl rs vs agnd WM8143-10 vmid offset offset op[9:0] pga pga 5-bit reg cds 5-bit reg 5-bit reg pga vmid vmid cds cds s/h s/h s/h s/h s/h s/h 8-bit + sign dac 8-bit + sign dac 8-bit + sign dac
WM8143-10 production data wolfson microelectronics pd rev 3f june 98 2 pin configuration ordering information device temp. range package WM8143-10cft/v 0 - 70 o c 32 pin tqfp 1 8 7 6 5 4 3 2 op[0] op[6] op[5] op[4] op[3] op[2] op[1] op[7] 25 32 31 30 29 28 27 26 sck/rnw nc nc dgnd mclk vsmp rlc dvdd 24 17 18 19 20 21 22 23 sdi/dna vrlc binp ginp rinp oeb sen/stb vmid 16 9 10 11 12 13 14 15 vrt op[9] nreset avdd agnd vru vrb op[8] WM8143-10 absolute maximum ratings analogue supply voltage .......... agnd - 0.3v, agnd +7v digital supply voltage ............... dgnd - 0.3v, dgnd +7v digital inputs .......................... dgnd - 0.3v, dvdd +0.3v digital outputs ....................... dgnd - 0.3v, dvdd +0.3v reference inputs .................... agnd - 0.3v, avdd +0.3v rinp, ginp, binp .................. agnd - 0.3 v, avdd + 0.3v operating temperature range, t a .......... 0 c to +70 c storage temperature .......................... -50 c to +150 c lead temperature (soldering 10 seconds) ....... +260 c absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. as per jedec specifications a112-a and a113-a, this product requires specific storage conditions prior to surface mount assembly. it has been classified as having a moisture sensitivity level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. recommended operating conditions parameter symbol test conditions min typ max unit supply voltage avdd, dvdd 4.75 5.25 v operating temperature range t a 0 70 o c input common mode range v cmr 0.5 4.5 v production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 3 electrical characteristics test characteristics avdd = dvdd = 4.75v to 5.25v, agnd = dgnd = 0v ? t a = 0 o c to +70 o c, mclk = 12mhz, unless otherwise stated parameter symbol test conditions min typ max unit supply current - active 100 140 ma supply current - standby 7 15 ma digital inputs high level input voltage v ih 0.8*dvdd v low level input voltage v il 0.2*dvdd v high level input current i ih 1 a low level input current i il 1 a input capacitance 5 pf digital outputs high level output voltage v oh i oh = 1ma dvdd-0.75 v low level output voltage v ol i ol = 1ma dgnd+0.75 v high impedance output current i oz 1 a input multiplexer cds mode full scale input range (v vs -v rs ) x denotes the channel selected 2 gx vp-p channel to channel gain matching 1 % input video set-up time tvsu 10 ns input video hold time tvh 15 ns reset video set-up time trsu cds mode only 10 ns reset video hold time trh cds mode only 15 ns reference string reference voltage ? top vrt vru = 5v 3.47 3.5 3.53 v reference voltage ? bottom vrb vru = 5v 1.47 1.5 1.53 v dac reference voltage vmid vru = 5v 2.47 2.5 2.53 v r.l.c. switching impedance 500 w 1.46 1.5 1.54 v 2.46 2.5 2.54 v reset level clamp options vrlc vru=5v voltage set by register configuration 3.46 3.5 3.54 v impedance vrt to vrb 250 500 750 w impedance vru to agnd 1000 1500 2000 w 8-bit dacs resolution 8 bits zero code voltage v mid -20 v mid +20 mv full scale voltage error 0 20 mv WM8143-10 production data wolfson microelectronics pd rev 3f june 98 4 test characteristics avdd = dvdd = 4.75v to 5.25v, agnd = dgnd = 0v ? t a = 0 o c to +70 o c, mclk = 12mhz, unless otherwise stated parameter symbol test conditions min typ max unit differential non linearity dnl 0.1 0.5 lsb integral non linearity inl 0.25 1 lsb 10-bit adc performance including cds, pga and offset functions no missing codes guaranteed resolution avdd = dvdd = 5v 10 bits maximum sampling rate avdd = dvdd = 5v 6 msps zero scale transition error voltage at vinp dac code = 000h, avdd = dvdd = 5v, measured relative to vrb 25 100 mv full scale transition error voltage at vinp dac code = 000h, avdd = dvdd = 5v, measured relative to vrt 25 100 mv differential non linearity dnl avdd = dvdd = 5v +1 lsb pga gain monotonicity guaranteed red channel max gain gr 7 7.5 times green channel max gain gg 7.5 8 times blue channel max gain gb mode 1 avdd = dvdd = 5v 7.5 8 times switching characteristics mclk period tper 83.3 ns mclk high tckh 37.5 ns mclk low tckl 37.5 ns data set-up time tdsu 10 ns data hold time tdh 10 ns output propagation delay tpd i oh =1ma, i ol =1ma 75 ns output enable time tpze 50 ns output disable time tpez 25 ns serial interface sck period tsper 83.3 ns sck high tsckh 37.5 ns sck low tsckl 37.5 ns sdi set up time tssu 10 ns sdi hold time tsh 10 ns set up time - sck to sen tsce 20 ns set up time - sen to sck tsec 20 ns production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 5 test characteristics avdd = dvdd = 4.75v to 5.25v, agnd = dgnd = 0v ? t a = 0 o c to +70 o c, mclk = 12mhz, unless otherwise stated parameter symbol test conditions min typ max unit sen pulse width tsew 50 ns parallel interface rnw low to op[9:2] tri-state topz 20 ns address setup time to stb low tasu 0 ns dna low setup time to stb low tadls 10 ns strobe low time tstb 50 ns address hold time from stb high tah 10 ns dna low hold time from stb high tadlh 10 ns data setup time to stb low tdsu 0 ns dna high setup time to stb low tadhs 10 ns data hold time from stb high tdh 10 ns data high hold time from stb high tadhh 10 ns rnw high to op[9:2] output topd 0 ns WM8143-10 production data wolfson microelectronics pd rev 3f june 98 6 pin description pin name type description 1 op[0] digital op tri-state digital 10-bit bi-directional bus. there are four modes: 2 op1] digital op tri-state: when oeb = 1 3 op[2] digital io 4 op[3] digital io 5 op[4] digital io 6 op[5] digital io 7 op[6] digital io 8 op[7] digital io 9 op[8] digital io 10 op[9] digital io output ten-bit: ten bit data is output from bus output 8-bit multiplexed: data output on op[9:2] at 2 * adc conversion rate input 8-bit: control data is input on bits op[9:2] in parallel mode when sck/rnw = 0. msb of the output word is op[9], lsb is op[0] 11 nreset digital ip reset input, active low. this signal forces a reset of all internal registers and selects whether serial control bus or parallel control bus is used ( see sen/stb) 12 avdd analogue supply positive analogue supply (5v) 13 agnd analogue supply analogue ground (0v) 14 vru analogue ip 15 vrb analogue op 16 vrt analogue op adc reference voltages. the adc reference range is applied between v rt (full scale) and v rb (zero level). v ru can be used to derive optimal reference voltages from an external 5v reference 17 vmid analogue op buffered mid-point of adc reference string. 18 vrlc analogue op selectable analogue output voltage for rlc 19 binp analogue ip blue channel input video 20 ginp analogue ip green channel input video 21 rinp analogue ip red channel input video 22 oeb digital ip output tri-state control: all outputs enabled when oeb=0 23 sen/stb digital ip serial interface: enable, active high parallel interface: strobe, active low latched on nreset rising edge: if low then device control is by serial interface, if high then device control is by parallel interface 24 sdi/dna digital ip serial interface: serial interface input data signal parallel interface: high = data, low = address 25 sck/rnw digital ip serial interface: serial interface clock signal parallel interface: high = op[9:2] is output bus low = op[9:2] is input bus 26 rlc digital ip selects whether reset level clamp is applied on a pixel-by-pixel basis. if rlc is required on each pixel then this pin can be tied high 27 vsmp digital ip video sample synchronisation pulse. this signal is applied synchronously with mlck to specify the point in time that the input is sampled. the timing of internal multiplexing between the r, g and b channels is derived from this signal 28 mclk digital ip master clock. this clock is applied at eight , six, three or two times the input pixel rate depending on the operational mode. mclk is divided internally to define the adc sample rate and to provide the clock source for digital logic production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 7 pin name type description 29 dgnd digital supply digital ground (0v) 30 nc reserved, pin must be left unconnected 31 nc reserved, pin must be left unconnected 32 dvdd digital supply positive digital supply (5v) typical performance avdd = dvdd = 5v, t a = 25 o c pga gain code vs actual gain 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 8.25 0 1 2 3 4 5 6 7 8 9 actual gain pga gain code red green blue WM8143-10 dnl -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 256 512 768 1024 adc code lsb's WM8143-10 production data wolfson microelectronics pd rev 3f june 98 8 system description red green blue colour ccd sensor buffering for ccd op[9:0] oeb sdi/dna sck/rnw nreset sen/stb vsmp mclk rlc WM8143-10 rinp ginp binp parallel data i/o control/serial data in analogue interface timing figure 1 system diagram the WM8143-10 signal processing ic interfaces typically via buffering and ac coupling to the output of ccd image sensors. the WM8143-10 also interfaces to cis image sensors via dc coupling. analogue output signals from the image sensor are sampled, amplified and offset-corrected by the ic before being converted into digital form by an on-board high-speed 10-bit resolution analogue to digital converter. figure 1 illustrates a typical system implementation where the three colour outputs from the ccd image sensor are buffered and ac coupled to the analogue inputs of the WM8143-10. the digital interface to the WM8143-10 can be divided into three distinct sections: - parallel data i/o digital control/serial timing analogue interface timing these sections are constructed for ease of use by the system designer and are described in detail on the following pages of this datasheet. production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 9 device description s/h, offset dacs and pga each analogue input (rinp, ginp, binp) of the WM8143-10 consists of a sample and hold, a programmable gain amplifier, and a dc offset correction block. the operation of the red input stage is summarised in figure 2. s/h s/h gain=g vs vmid v adc vmid v offset rinp rs - + + + figure 2 operation of red input stage the sample/hold block can operate in two modes of operation, cds (correlated double sampling) or single ended. in cds operation the video signal processed is the difference between the voltage applied at the rinp input when rs occurs, and the voltage at the rinp input when vs occurs. this is summarised in figure 3 . figure 3 video signal processed in cds mode when using cds the actual dc value of the input signal is not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. this is because the signal processed is the difference between the two sample voltages, with the common dc voltage being rejected. in single ended operation, the vs and rs control signals occur simultaneously, and the voltage applied to the reset switch is fixed at v mid . this means that the voltage processed is the difference between the voltage applied to rinp when vs/rs occurs, and v mid . when using single ended operation the dc content of the video signal is not rejected. the programmable gain amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface. table 1 illustrates the pga gains register codes required for typical gains. (see typical performance graphs). the typical gain may also be calculated using the following equation: typical gain = 0.5+(code *0 .25). code typical gain code typical gain 00000 0.5 10000 4.5 00001 0.75 10001 4.75 00010 1 10010 5 00011 1.25 10011 5.25 00100 1.5 10100 5.5 00101 1.75 10101 5.75 00110 2 10110 6 00111 2.25 10111 6.25 01000 2.5 11000 6.5 01001 2.75 11001 6.75 01010 3 11010 7 01011 3.25 11011 7.25 01100 3.5 11100 7.5 01101 3.75 11101 7.75 01110 4 11110 8 01111 4.25 11111 8.25 table 1 typical gain the dc value of the gained signal can then be trimmed by the 8 bit plus sign dac. the voltage output by this dac is shown as v offset in figure 2. the range of the dac is (v mid /2) or 1.5*(v mid /2) if the dac_range bit in set-up register 4 is set. the output from the offset dac stage is referenced to the v mid voltage. this allows the input to the adc to maximise the dynamic range, and is shown diagrammatically in figure 2 by the final v mid addition. rs vs v rs v vs WM8143-10 production data wolfson microelectronics pd rev 3f june 98 10 for the input stage, the final analogue voltage applied to the adc can be expressed as: where v adc is the voltage applied, to the adc g is the programmed gain v vs is the voltage of the video sample. v rs is the voltage of the reset sample , dsign is the offset dac sign bit dac_code is the offset dac value. v mid is the WM8143-10 generated vmid voltage. the adc has a lower reference of v rb (typically 1.5 v) and an upper reference of v rt (typically 3.5 v). when an adc input voltage is applied to the adc equal to v rb the resulting code is 000(hex). when an adc input voltage is applied to the adc equal to v rt the resulting code is 3ff(hex). reset level clamp both cds and single ended operation can be used with reset level clamping. a typical input configuration is shown in figure 4. WM8143-10 s/h s/h gain=g vs vmid vrlc rinp cin rs - + figure 4 typical input configuration using reset level clamping the position of the clamp relative to the video sample is shown diagramatically in figure 6 and is programmable by cdsref1-0 (see table 6). by default, the reset sample occurs on the fourth mclk rising edge after vsmp. the relative timing between the reset sample (and cl) and video sample can be altered as shown in figure 5. when the clamp pulse is active the voltage on the WM8143-10 side of cin, i.e. rinp, will be forced to be equal to the vrlc clamp voltage. the vrlc clamp voltage is programmable to three different levels via the serial interface. the voltage to which the clamp voltage should be programmed is dependent on the type of sampling selected and the polarity of the input video signal. 00 10 11 01 (default) vs rs rs rs cl cl cl vsmp mclk cl rs figure 5 reset sample and clamp timing for cds operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. this will allow the best use of the wide input common-mode range offered by the WM8143-10. if the input video is positive going it is advisable to clamp to vcl (lower clamp voltage). if the video is negative going it is advisable to clamp to vcu (upper clamp voltage). regardless of where the video is clamped the offset dac is programmed to move the adc output corresponding to the reset level to an appropriate value to maximise the adc dynamic range. for single ended operation it is recommended that the clamp voltage is set to vcm (middle clamp voltage). clamp pulse video input figure 6 position of clamp relative to video input a reset level clamp is activated if the rlc pin is high on an mclk rising edge (figure 7). by default this initiates an internal clamp pulse three mclk pulses later (shown as cl in figure 5). the relationship between cl and rs is fixed. therefore altering the rs position also alters the cl position (figure 5). table 6 shows the three possible voltages to which the reset level can be clamped. mid rs vs adc v 2 v * 255 dac_code * dsign) * 2 (1 ) v (v * g v ] [ mid + - + - = production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 11 mclk 1 x x 0 0 x x x input video vsmp rlc r ,g,b r ,g,b rlc on this pixel no rlc on this pixel r ,g,b figure 7 rlc timing video sampling options the WM8143-10 can interface to ccd sensors using six basic modes of operation (summarised in table 3). mode configurations are controlled by a combination of control bits and timing applied to mclk and vmsp pins. the default operational mode is mode 1: colour with cds enabled. colour mode definitions (mode 1) figure 9 summarises the timing relationships. mclk is applied at twice the required adc conversion rate. synchronisation of sampling and channel multiplexing to the incoming video signal is performed by the vsmp pulse (active high). the three input channels (r,g,b) are sampled in parallel on the rising edge of mclk following a vsmp pulse. the sampled data is multiplexed into a single data stream at three times the vsmp rate, passes through the internal pipeline and emerges on the op[9:0] bus. both correlated double sampling (cds) and single ended sampling modes of operation are available. monochrome mode definitions one input channel is continuously sampled on the rising edge of mclk following a vsmp pulse. the user can specify which input channel (r ,g,b) is to be sampled by writing to the WM8143-10 internal control registers. there are four separate monochrome modes with different maximum sample rates and cds availability. monochrome mode (mode 2) figure 10 summarises the timing relationships. the timing in this mode is identical to mode 1 except that one input channel is sampled three times (due to the multiplexer being held in one position) and passes through the device as three separate samples. the last two samples can be ignored at the output op[9:0]. fast monochrome mode (mode 3) figure 11 summarises the timing relationships. this mode allows the maximum sample rate to be increased to 4 msps. this is achieved by altering the mclk :vsmp ratio to 3:1. in this mode, the timing of rs and cl must be fixed (refer to table 3). the sampled video data will pass through the internal pipeline and emerge on the op[9:0] bus. max. speed monochrome mode (mode 4) figure 12 summarises the timing relationships. this mode allows the maximum sample rate to be increased to 6 msps. this is achieved by altering the mclk :vsmp ratio to 2:1. the latency through the device is identical to modes 1 and 2. cds is not available in this mode. slow colour mode (mode 5) figure 13 summarises the timing relationships. this mode is identical to mode 1 except that the mclk to vsmp ratio is 8 : 1 and the maximum sample rate is 1.5 msps. to obtain a ratio of 4:4 between the video sample position and the reset sample position, setup register 3 cdsref1-0 control bits b[5:4] should be set to 10. the first three of the four output words are valid. slow monochrome mode (mode 6) figure 14 summarises the timing relationships. this mode is identical to mode 2 except that the mclk to vsmp ratio is 8 : 1 and the maximum sample rate is 1.5 msps. to obtain a ratio of 4:4 between the video sample position and the reset sample position, setup register 3 cdsref 1-0 control bits b[5:4] should be set to 10. the first of the four output words is the only valid output. input impedance the input impedance of the WM8143-10 is dependent upon the sampling frequency of the input signal and the gain that the pga is set to. this is due to the effective capacitance of the ?sample and hold? circuits (figure 8) . rinp/vmid pga vs/rs c vmid s/h figure 8 input impedance s/h circuit when the vs/rs control is activated the switch closes and the effective impedance of the input is 1/cf where the value of c changes from 0.3pf for minimum gain to WM8143-10 production data wolfson microelectronics pd rev 3f june 98 12 9.6pf for maximum gain and f is the sample frequency in hz. table 2 illustrates the maximum and minimum input impedance at different frequencies. sampling frequency (mh z ) impedance (m w w ) min. gain impedance ( k w w ) max. gain 0.5 6.6 208 1 3.3 104 2 1.6 52 4 0.8 26 6 0.5 17 table 2 effects of frequency on input impedance calibration to achieve optimum performance of the WM8143-10, a calibration procedure must be implemented. this is achieved by using a combination of the gain and offset functions to amplify and shift the input signal so that it lies within and maximises the input adc range. production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 13 mode description cds avail- able max. sample rate sensor interface description timing require- ments register contents with cds register contents without cds* 1 colour yes 2msps three input channels (r, g, b) are sampled in parallel at max. 2msps. the sampled data is multiplexed into a single data stream before the internal adc, giving an internal serial rate of max. 6msps mclk max. 12mhz. mclk: vsmp ratio is 6:1 setup reg. 1: 03(h) setup reg. 1: 01(h) 2 monochrome yes 2msps one input channel is continuously sampled. the internal multiplexer is held in one position under control of the user. identical to mode 1 setup reg. 1: 07(h) setup reg. 3: bits b[7-6] define which channel is sampled setup reg. 1:05(h) setup reg. 3: bits b[7-6] define which channel is sampled 3 fast monochrome yes 4msps identical to mode 2 except that max. sample rate is 4msps mclk max. 12mhz. mclk: vsmp ratio is 3:1 identical to mode 2 plus setup reg. 3: bits b[5-4] must be set to 00(h) identical to mode 2 4 max. speed monochrome no 6msps identical to mode 2 except that max. sample rate is 6msps mclk max. 12mhz. mclk: vsmp ratio is 2:1 not applicable setup reg. 1:45(h) setup reg. 3: bits b[7-6] define which channel is sampled 5 slow colour yes 1.5msps identical to mode 1 except that max. sample rate is 1.5msps mclk max. 12mhz. mclk: vsmp ratio is 8:1 identical to mode 1 identical to mode 1 6 slow monochrome yes 1.5msps identical to mode 2 except that max. sample rate is 1.5msps mclk max. 12mhz. mclk: vsmp ratio is 8:1 identical to mode 2 identical to mode 2 * only indicates relevant register bits table 3 WM8143-10 mode summary WM8143-10 production data wolfson microelectronics pd rev 3f june 98 14 adc input adc sample vs rs input video vsmp mclk op[9:0] input signals internal signals output signals r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 b0 g1 r1 16.5 mclk periods g2 r2 g3 r3 b1 b2 b3 r4 g4 b4 1 2 3 4 5 2 3 4 5 r1 g1 b1 figure 9 default timing in cds colour mode (mode 1) adc input adc sample vs rs input video vsmp mclk op[9:0] * input signals internal signals output signals r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 x x r1 16.5 mclk periods x x x x x x x 1 2 3 4 5 2 3 4 5 * this example shows function when red channel selected. 'x' indicates don't care r1 x x x x x x x x x figure 10 default timing in cds monochrome mode (mode 2) production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 15 adc input adc sample vs rs input video vsmp mclk op[9:0] input signals internal signals output signals n n n n+1 23.5 mclk periods * this example shows function when red channel selected. figure 11 default timing in fast cds monochrome mode (mode 3) adc sample input video input signals internal signals output signals * this example shows function when red channel selected. adc input vs vsmp mclk n 16.5 mclk periods n 1 op[9:0] n figure 12 default timing in max. speed non-cds monochrome mode (mode 4) WM8143-10 production data wolfson microelectronics pd rev 3f june 98 16 adc input adc sample vs rs input video vsmp op[9:0] input signals internal signals output signals r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 16.5 mclk periods 1 2 3 4 5 2 3 4 5 mclk g2 b0 g1 r1 r2 x b2 b1 r3 g3 b3 x x b4 g4 r4 x 'x' indicates an invalid output r1 g1 b1 x figure 13 default timing in slow cds colour mode (mode 5) adc input adc sample vs rs input video vsmp op[9:0] input signals internal signals output signals r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 16.5 mclk periods 1 2 3 4 5 2 3 4 5 r1 mclk x x x this example shows function when red channel selected. 'x' indicated invalid output. x b0 x r1 r2 x x x r3 x x x x x x r4 x figure 14 default timing in slow monochrome mode (mode 6) production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 17 applications recommendations output data interface by default, data is output from the device as a ten-bit wide word on op[9:0]. optionally, data can be output in an eight-bit word format. figure 15 shows this function. data is presented on pins op[9:2] at twice pixel rate. in mode 3, the output is spread over three mclk periods. the first two periods contain byte a data and the third period has byte b data. either of the two byte a data periods are valid. figure 15 eight-bit multiplexed bus output a =d9,d8,d7,d6,d5,d4,d3,d2 - first byte b =d1,d0,x,x,pns,cc1,cc0,orng - second byte pns : this bit shows if the device is configured in parallel or serial mode. 1 = parallel, 0 = serial. cc1/ cc0 : these bits show which channel the current output was taken from. 00 = red, 01 = green, 10 = blue. orng : this bit indicates if the current output pixel has exceeded the maximum or minimum range during processing. 1 = out of range, 0 = within range . x: this is an invalid output. control interface selection WM8143-10 can be controlled via a serial or parallel interface. the decision on which interface is to be used is made on the sense of the sen/stb pin on the rising edge of the nreset signal. sen/stb condition mode 0 nreset rising edge serial interface 1 nreset rising edge parallel interface table 4 WM8143-10 interface set-up it is expected that this would be achieved on system power-up by attaching a simple rc network to the nreset pin. the rc network should delay the set-up on the nreset pin until the other conditions have been established. this feature is only activated on a hardware reset (using the nreset pin). the software reset does not sample sen/stb. controlling the WM8143-10 the WM8143-10 can be configured through a serial interface or a parallel interface. selection of the interface type is by the sen/stb pin which must be tied high (parallel) or low (serial) as shown in table 4. serial interface the serial interface consists of three pins (refer to figure 16). a six-bit address is clocked in msb first followed by an eight-bit data word, also msb first. each bit is latched on the rising edge of sck. once the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. parallel interface the parallel interface uses bits [9:2] of the op bus as well as the stb, dna and rnw pins (refer to figure 17). pin rnw must be low during a write operation. the dna pin defines whether the data byte is address (low) or data (high). the data bus op[9:2] is latched in during the low period of stb. internal register definition table 5 summarises the internal register content. the first 5 addresses in the table are used to program setup registers and to provide a software reset feature (00h is reserved). the remaining 3 entries in the table define the address location of internal data registers. in each case, a further three sub-addresses are defined for the red, green and blue register. selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. blank entries in table 5 should be programmed to zero. a4 a5 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 sck sdi sen data word address figure 16 serial interface timing a b mclk op[9:2] WM8143-10 production data wolfson microelectronics pd rev 3f june 98 18 figure 17 parallel interface timing bit address production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 19 register bit no bit names(s) default description 0 enadc 1 adc standby control: 0 = standby, 1 = active 1 cds 1 correlated double sampling mode: 0 = single ended mode, 1 = cds mode 2 mono 0 mono/ colour select: 0 = colour, 1 = monochrome operation setup register 1 address , WM8143-10 production data wolfson microelectronics pd rev 3f june 98 20 detailed timing diagrams tvsu tvsu tdsu tdh trsu trh tvh tvh mclk vsmp, rlc r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) r,g,b video inputs (default mode) r,g,b video inputs (cdsref[1]=0,cdsref[0]=1) r,g,b video inputs (cdsref[1]=1,cdsref[0]=0) r,g,b video inputs (cdsref[1]=1,cdsref[0]=1) tdsu tdh tvsu tvh tvsu tvh tvsu tvh trsu trh trsu trh trsu trh tvsu tvh tvsu tvh tvsu tvh tvsu tvh figure 18 detailed video input timing - modes 1 and 2 tdsu tvsu trsu tdh tvh trh mclk vsmp, rlc r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) tdsu tdh tvsu tvh figure 19 detailed video input timing - mode 3 t dsu t vsu t dh t vh mclk vsmp, rlc r,g,b video inputs t vsu t vh video reset figure 20 detailed video input timing - mode 4 production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 21 mclk vsmp, rlc tdsu tdh tdsu tdh tvsu tvsu trsu trh tvh tvh tvsu tvh tvsu tvh tvsu tvh trsu trh trsu trh trsu trh tvsu tvh tvsu tvh tvsu tvh r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) r,g,b video inputs (cdsref[1]=0,cdsref[0]=0) figure 21 detailed video timing - modes 5 and 6 tdsu tdh mclk op[9:0] tper t ckh t ckl t pd red green blue vsmp, rlc figure 22 detailed digital timing - modes 1 and 2 tdsu tdh mclk vsmp, rlc op[9:0] tper t ckh t ckl t pd tdsu tdh t pd figure 23 detailed digital timing ? mode 3 WM8143-10 production data wolfson microelectronics pd rev 3f june 98 22 tds u td h mclk vsmp, rlc op[9:0] tper t ckh t ckl t pd tds u td h t pd figure 24 detailed digital timing ? mode 4 tdsu tdh mclk vsmp, rlc op[9:0] tper t ckh t ckl t pd red green blue x 'x' indicates invalid output x figure 25 detailed digital timing ? modes 5 and 6 tsckh tsckl tssu tsh tsce tsew tsec tsper sck sdi sen figure 26 detailed timing diagram for serial interface rnw dna op[9:2] stb data out z address in tadls tasu tstb tadhs tadlh tdsu tah data in tadhh tdh topd z data out tstb topz figure 27 detailed timing diagram for parallel interface production data WM8143-10 wolfson microelectronics pd. rev 3f june 98 23 applications diagram 1 8 7 6 5 4 3 2 25 32 31 30 29 28 27 26 sck/rnw nc nc dgnd mclk vsmp rlc dvdd 24 17 18 19 20 21 22 23 sdi/dna vrlc binp ginp rinp oeb sen/stb vmid 16 9 10 11 12 13 14 15 vrt nreset avdd agnd vru vrb WM8143-10 avdd agnd 100nf 10 m f 100nf 10 m f 100nf 10 m f 10 m f + + + + 100nf 22 m f 100nf + + 100nf 10 m f dvdd dgnd 100nf + 10 m f note: agnd and dgnd should be starpointed as close as possible to the agnd pins op[0] op[6] op[5] op[4] op[3] op[2] op[1] op[7] op[9] op[8] WM8143-10 production data wolfson microelectronics pd rev 3f june 98 24 package dimensions 1 8 9 16 17 24 25 32 0.80 bsc 1.60max 1.45 1.35 0.10 seating plane 7.00 bsc 9.00 bsc 0.45 0.30 0.20 m dm002.a 32-pin tqfp 0.15 0.05 0.25 0.75 0.45 0 o - 7 o 0.20 0.09 gauge plane notes: a. all linear dimensions are in milimeters b the drawing is subject to change without notice c falls within jedec ms-026. refer to this specification for further details. last page of WM8143-10 datasheet |
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